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Errors in The Essentials of Computer Organization and Architecture
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Textbook Errata: Second Edition (2006)

This file documents the additional errors and misinformation found in
the above book.  Many of these errors were also in the First Edition.

See the publisher's web site for their own list of errata:

http://www.jbpub.com/
http://computerscience.jbpub.com/ecoa/2e/
http://www.jbpub.com/samples/0763737690/errata-ecoa2e-june-2007-1.pdf
http://www.jbpub.com/samples/0763737690/errata-ecoa2e-june-2007-2.pdf

The errors below are *in addition* to the above publisher errors:

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Chapter 4 errors
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p.199
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Replace the odd fetch/decode/execute steps 1-4 with this new trio:

   1. fetch from memory (at location in PC), the instruction into the IR
   2. increment PC by length of instruction
   3. execute instruction from IR

Here are the three in detail:

1. FETCH: Via the PC, fetch the next instruction from memory into the IR.

   RTN/RTL for the above FETCH:
     Copy the contents of the PC to the MAR:  MAR <-- PC
     Read instruction from memory into MBR:   MBR <-- M[MAR]
     Copy instruction from MBR into IR:       IR <-- MBR
     (Note: The text may show M[MAR] going directly into the IR.)

2. INCREMENT: Increment the PC by the length of the instruction just fetched.

   RTN/RTL for the above INCREMENT:
     Add one to the PC:   PC <-- PC + 1
   (For MARIE, all instructions have the same length of "1" word.
   This uniform length is not true of all instruction set architectures.)

3. EXECUTE: Perform the instruction.

   RTN/RTL for EXECUTE (depends on the instruction):
     Decode the opcode field in the IR.  Based on the value of the opcode,
     execute the RTN sub-instructions needed to perform the operation.
     If the instruction uses an address, place the address field of the
     IR (bits 11-0) into the MAR and read or write that address in memory.
     Not all instructions access memory.  Not all instructions use the
     IR "address field" as an address (e.g. Halt, Input, Output, Skipcond).

Fix the flow chart Figure 4.11 p.200 to correspond to the above steps.
In particular, fix the "Yes" box to indicate that the copy could be from
memory to MBR (e.g. Load) or from MBR to memory (e.g. Store).

p.205
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The book is inconsistent in its use of the MBR.  The bus architecture in
Fig. 4.9 on p 192 shows that a value from memory can go directly into
any MARIE register; yet, the text shows LOAD X as going first into the
MBR and then into the AC but on p.205 data from memory goes directly
into the IR without passing through the MBR.  I'm confused.

p.210
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The book is inconsistent about where math operations can happen.
In Fig. 4.14 on p.205 we see that PC <-- PC+1, no AC required; but, on
p.210 we see that we have to use the AC to add both 1 and MBR to the PC:

    MBR <-- X
    AC <-- 1
    AC <-- AC + MBR
    PC <-- AC

Why didn't they simplify the above four-line mess (p.210) into just
these two lines:

    PC <-- X
    PC <-- PC + 1

I'm confused.

The MARIE simulator does not obey the textbook RTN given for JNS (and
the RTN in corresponding Power Point slide #49 also has a typo in it).

The text RTN for JNS uses the AC to add both 1 and MBR together before
storing the result from the AC into the PC.  The MARIE simulator doesn't
do that for JNS - the AC isn't changed at all, and the MBR is pointlessly
loaded with the memory value at X before the PC is stored there.  I think
both the text and MARIE are needlessly complex and possibly both wrong.
Here is my replacement, simplified RTN for JNS (three lines instead
of seven):

   MAR <-- X
   M[MAR] <-- PC   /store the PC into memory at address X
   PC <-- X + 1    /jump to location after X

Note that my simplified RTN above doesn't change the AC or MBR.
(The MARIE simulator will set MBR to M[MAR] before storing the PC there.)