========================================
Assignment #08 - CPU/Memory Architecture
========================================
- Ian! D. Allen - idallen@idallen.ca - www.idallen.com

1. How many address wires does it take to address 1GB of memory?
ANSWER: 1GB = 2**30 therefore 30 wires

2. How many address wires does it take to address 12GB of memory?
ANSWER: 12GB < 16GB and 16GB = 2**4 * 2**30 therefore 34 wires

3. How much memory (in GB) can be addressed by 32 address wires?
ANSWER: 2**32 = 2**2 * 2**30 = 4 GB

4. True/False: A bootloader can run entirely in ROM, without using any RAM.
Defend (give a reason for) your answer.
ANSWER: False
REASON: Variables used in the bootloader must reside in RAM, not ROM.

5. List three ways that a bootloader can determine the size of an
application program that it must read into memory:
ANSWER: (see 16LMCBootstrap.htm)
    1. fixed size 2. use a sentinel 3. prefix run-length

6. The register in the CPU used to hold an address being sent to Memory
is named (give the full name, not just the abbreviation):
ANSWER: Memory Address Register - MAR

7. The register in the CPU used to hold data going to or coming from Memory
is named (give the full name, not just the abbreviation):
ANSWER: Memory Data Register - MDR

8. In addition to the Clock Signal, the Control Bus between a CPU and memory
contains two other critical signals.  Name them:
ANSWER: Read/Write selection, Memory Enable

9. The register used to hold and remember an instruction between the Fetch
and Execute cycles is named:
ANSWER: Instruction Register - IR

10. Two names (synonyms) for the equivalent of the LMC "Counter" in a real
General Purpose computer are:
ANSWER: Program Counter - PC, Instruction Pointer - IP

11. Give the three-item Instruction Cycle for a General Purpose Computer
(not the LMC):
ANSWER:
    1 Load the instruction found in memory at the address in the PC
      (program counter) into the IR (instruction register)
    2 Increment the PC by the length of the instruction just loaded
      (this may be a fixed amount or it may vary depending upon the
      instruction and the specific processor)
    3 Execute the instruction in the IR
    Repeat from step 1

12. What is the "von Neumann Bottleneck"?
ANSWER: Processing speed in the general computer model is limited by the
   single-instruction-at-a-time fetch-decode-execute cycle. Specifically, the
   need to wait for instruction loading across the memory-processor bus slows
   program execution significantly. 

13. If a machine instruction uses 32 bits, with 6 bits used for opcode and
the remainder of the bits divided equally between a register specification
and a twos-complement immediate operand, then:

   a) how many different opcodes are possible?  ANSWER: 2**6 = 64
   b) how many different registers may be selected?
      ANSWER: (32-6)/2 = 13 bits and 2**13 = 2**3 * 2**10 = 8K = 8192
   c) what is the smallest (most negative) immediate operand?
      ANSWER: 13 bits means 8192 numbers, half negative: -(2**12) = -4096
   d) what is the largest (most positive) immediate operand?
      ANSWER: 13 bits means 8192 numbers, half positive: +(2**12 - 1) = +4095